长江存储取得突破：史上最高的TLC位密度！

聚焦于半导体行业的知名研究公司TechInsights表示，中国厂商——长江存储（YMTC）与长鑫存储（CXMT）均取得了重大技术突破。

在致态最新发布的TiPro9000硬盘中，TechInsights发现了长江存储的新一代Xtacking4.0 3D NAND芯片。技术分析表明，它的总栅极数高达294层，有着业界最高的TLC位密度！

毫无疑问，这是存储行业的一大步。TechInsights以“TechInsights Finds YMTC 2yy-layered 3D NAND—the Highest TLC Bit Density Ever!（TechInsights发现了长江存储2yy层级3D NAND—史上最高的TLC位密度！）”为题，发布了专题探讨。

目前，这篇内容正位于TechInsights官网首页的醒目位置，亦有彭博社等多篇报道引用。以下是其原文，并附上我们的翻译：

“Today, TechInsights found and confirmed China's Yangtze Memory Technology Corporation’s (YMTC) latest and most advanced chip, Xtacking4.x 2yyL 1 Tb 3D TLC NAND. This chip which has the highest number of vertical gates seen in a commercial product to date.”

今天，TechInsights找到并确认了中国长江存储科技公司（YMTC）最新且最先进的芯片：Xtacking4.x技术2yy层级1Tbit 3D TLC NAND。这颗芯片拥有迄今为止商业产品中最多的垂直栅极数量。

2yy层级Xtacking4.0芯片，图自ZOL

“YMTC successfully extended the Xtacking 4.0 memory architecture to 2yy-layered 3D NAND devices despite severe U.S. sanctions against the company. It’s the first 2yy-layered 3D NAND device TechInsights has found on the market.”

尽管美国对该公司实施了严厉制裁，长江存储仍成功地将晶栈Xtacking 4.0存储架构扩展到2yy层3D NAND器件中。这是TechInsights在市场上发现的第一款2yy层3D NAND产品。

长江存储2yy层级1Tbit TLC 3D NAND芯片，发现于致态TiPro9000固态硬盘中

“We’re in the process of sourcing 2yy-layer (for example 286L) products fabricated from Samsung and Micron. SK hynix’s 321-layer 4D PUC NAND devices are expected to be on the market in H1 2025 as per TechInsights’3D NAND Technology Roadmap. Yet, the important takeaway is that China’s YMTC has beat the competition to the market with the TLC bit density found in this device.”

我们正在采购由三星和美光制造的2yy层级（如286层）产品。根据TechInsights的3D NAND技术路线图，SK海力士的321层4D PUC NAND器件预计将在2025上半年上市。然而，重要的地方在于：凭借其器件的TLC位密度优势，中国的长江存储已率先在市场竞争中占据领先地位。

3D NAND的位密度发展趋势（包括TLC和QLC）

“YMTC’s new Xtacking4.x chip, torn down from the ZhiTai SSD TiPro9000 ZTSS3CB08B34MC, has the YMTC Xtacking4.x structure and design. It consists of 2yy active layers (294L total gates except SGD), 150 gates for the lower deck, and 144 for the upper deck. YMTC maintains its direct bonding (hybrid-bonded) Xtacking structure with two wafers.”

长江存储的新型Xtacking4.x芯片，是从致态TiPro9000固态硬盘（ZTSS3CB08B34MC）中拆解而来的，拥有长江存储Xtacking4.x的结构与设计。它由2yy个有源层（除漏极选择栅极SGD外，总栅极数为294层）组成，下层拥有150个栅极，而上层则有144个栅极。长江存储保持了其两片晶圆直接键合（混合键合）的Xtacking结构。

每个3D垂直NAND String中的总栅极数量对比

“The previous Xtacking4.0 160L TLC structure consists of 180 total gates including selectors and dummy gates (except SGD). Vertical channel layouts differ slightly from the previous Xtacking4.0 160L; however, the TLC NAND bit density increases to more than 20 Gb/mm2 for the first time in the industry. We estimate the number of active WLs would be around 270.”

此前的Xtacking4.0 160层TLC结构共计包含180个栅极，其中包括选择器和虚拟栅极（漏极选择栅极SGD除外）。2yy层级芯片的垂直沟道布局与之前的160层Xtacking4.0略有不同；然而，其TLC NAND的位密度增至20Gbit/mm^2以上，这在业界尚属首次。我们估计，有效字线（WL）的数量约为270个。

（译者注：《黑神话·悟空》联名版TiPlus7100硬盘，便使用了TechInsights所提及的160层Xtacking4.0颗粒——与普通Tiplus7100不同）

“The YMTC 2yyL 1 Tb 3D NAND die design shows a Center-XDEC design, and the select gate (Poly-Si) on the drain side (SGD) is integrated separately on top of the cell array gates. The backside source connect (BSSC) scheme is still used for the 2yyL structure.”

长江存储2yy层级1Tbit 3D NAND芯片采用了中心译码器（Center-XDEC）设计，漏极侧的选择栅极（多晶硅，即SGD）被单独集成在存储单元阵列的栅极上方。2yy层结构仍然采用了背面源极连接（BSSC）的方案。

（译者注：“中心译码器”有助于减少位线电容，降低tRC延迟，据称可提升15%~20%性能。长江存储在Xtacking3.0时代引入了这项设计。）

Xtacking3.0芯片的XDEC示意图

“When YMTC released Xtacking4.0 devices (for example, 160L) last year,we expected YMTC would combine Xtacking4.0 technology with higher layers such as 2xxL and 2yyL. Because of the U.S. ban, YMTC has been unable to extend 3D NAND fabs and import advanced semiconductor equipment and tools. They needed a detour.

With the new Xtacking4.0 technology, YMTC appears to have found a way to overcome the current bans with this new chip. ”

当长江存储去年发布Xtacking4.0器件（如160层）时，我们便预计长江存储会将Xtacking4.0技术与更高的堆叠层级相结合，例如2xx层与2yy层。由于美国的禁令，长江存储一直无法扩建3D NAND晶圆厂，也无法进口先进的半导体设备与工具。他们需要绕道而行。

借助全新的Xtacking4.0技术，长江存储似乎已经找到了一条道路，通过新的芯片克服现有禁令。

160层Xtacking4.0芯片的特殊“双峰”符号。TechInsights认为，这与长江存储转向国产设备与材料的战略密切相关。

“Our technical analysis teams will continue digging into the materials, process integration, and chip design and publishing our findings on the TechInsights Platform as they come available. Please stay tuned.”

我们的技术分析团队将继续深入剖析材料、工艺集成及芯片设计细节，并将在TechInsights平台陆续发布相关研究成果。敬请关注！